As semiconductor devices become highly integrated, issues such as leakage current and punch through may arise. One way of addressing these issues is to use silicon on insulator (SOI) substrate according to conventional technology as illustrated in FIG. 1.
Referring to FIG. 1, a conventional SOI substrate has a structure where an insulation layer 3 and a silicon layer 5 are sequentially stacked on a semiconductor substrate 1. The insulation layer 3 is formed of a thermal oxide and the semiconductor substrate 1 and the silicon layer 5 are formed of a silicon single crystalline. In order to fabricate the SOI substrate, a first silicon substrate 1 having a thermal oxide layer 3 is attached to a second silicon substrate 5, and then a lower part of the second silicon substrate is removed by a planarization process. In a subsequent process, a field oxide layer is formed to contact with the insulation layer 3 in the silicon layer 5 to address the problem of leakage current that may occur during an operation of a transistor. However, the SOI may be expensive since two silicon wafers are used. Additionally, since a transistor is isolated by the insulation layer 3 and a field oxide layer, heat or a hot carrier may not be removed. Furthermore, it may be difficult to apply a back bias.
According to another conventional technology, a path can be formed to provide for the emission of heat or a hot carrier (or for applying a back bias) as illustrated in FIG. 2. Referring to FIG. 2, the silicon layer 5 and the insulation layer 3 in FIG. 1 are sequentially patterned to form an opening partially exposing the semiconductor substrate 1. An epitaxial layer 7 is grown from the exposed semiconductor substrate 1 in the opening to fill the opening. As illustrated in FIG. 2, while the epitaxial layer 7 is grown, a defect (D) may occur at the insulation layer 3, and a void (V) may be formed in the epitaxial layer 7. In the case that the void (V) is very large, the epitaxial layer 7 may not provide an adequate electrical path between the silicon layer 5 and the semiconductor substrate 1. This may result in a reduction in the reliability of the semiconductor substrate.